1. Field of the Invention
This invention relates to field of microprocessors and more particularly to a microprocessor employing a data cache with mechanisms for line locking and line addressable disabling of write-through operations.
2. Description of the Related Art
Microprocessor based systems typically include cache memories to improve the average bandwidth of memory transactions. A cache memory may be configured as an internal or external cache. An internal cache, i.e. a cache embedded within the microprocessor substrate, may be accessed faster than an external cache, however due to the necessity to conserve die area, an internal cache has significantly less storage capacity than an external cache. Many microprocessor based systems employ both an internal cache and external cache. Also, microprocessors quite often employ two distinct internal caches: an instruction cache for accessing instructions, and a data cache for accessing data (operands).
In general, a cache memory is a high-speed memory unit interposed between a microprocessor (or microprocessor core) and a slower system memory. A cache memory operates according to the assumption that the microprocessor is likely to revisit, i.e. read or write, memory locations in the vicinity of a current access to system memory. Thus, in response to a memory access request asserted by the microprocessor (or microprocessor core), the cache memory reads a whole neighborhood of memory locations in the vicinity of the current access address into the cache memory provided this neighborhood is not already present in the cache memory. Future accesses to this address neighborhood are satisfied by the cache memory with greatly reduced access time.
A cache memory includes a plurality of lines, where each line stores two or more words of data. System memory is also viewed as being organized into consecutive lines. Each line of the cache memory has associated with it an address tag that uniquely identifies which line of system memory it is a copy of. When the microprocessor (or microprocessor core) asserts a memory read request, the cache memory performs an address tag comparison to determine whether a copy of the requested data resides in a line of the cache memory. If present, the data is accessed directly from the cache memory. This event is referred to as a cache read "hit". If not present, a line containing the requested data is retrieved from system memory and stored in the cache memory. The requested word is also supplied to the microprocessor. This event is referred to as a cache read "miss".
When the microprocessor asserts a write request, the cache memory performs an address tag comparison to determine whether the line into which data is to be written resides in the cache memory. If the line is present in the cache memory, the data is written directly into the line. This event is referred to as a cache write "hit". If the line into which data is to be written does not exist in the cache memory, the data is written to system memory, and the targeted line in system memory is fetched into the cache memory. This event is referred to as a cache write "miss". A line which is overwritten or copied out of the cache memory when new line of data is stored in the cache memory is referred to as a victim line.
Cache memories can be optimized according to a number of different techniques. One aspect that affects system performance and design complexity is the handling of writes operations. As explained previously, because two copies of a particular piece of data or instruction code can exist, one in system memory and a duplicate copy in the cache, writes to either the system memory or the cache memory can result in an incoherence between the two storage units. For example, consider the case in which the same data is initially stored at a predetermined address in both the cache memory and the system memory. If the processor subsequently initiates a write cycle to store a new data item at the predetermined address, a cache write "hit" occurs and the processor proceeds to write the new data into the cache memory at the predetermined address. Since the data is modified in the cache memory but not in system memory, the cache memory and system memory become incoherent.
An incoherence between the cache memory and system memory during processor writes can be prevented or handled by implementing one of several commonly employed techniques. In a first technique, a "write-through" cache guarantees consistency between the cache memory and system memory by writing the same data to both the cache memory and system memory. The contents of the cache memory and system memory are always identical, and thus the two storage systems are always coherent. In a second technique, a "write-back" cache handles processor writes by writing only to the cache memory, and setting a "dirty" bit associated with a cache line to indicate that one or more entries within the cache line have been altered by the microprocessor. The "dirty", i.e. altered line is later written back to system memory to re-establish coherency.
A microprocessor employing a cache memory experiences an average increase in memory access bandwidth and a consequent increase processing capacity. However, some critical processing tasks, especially in embedded microprocessor applications, require guaranteed fast memory access times. For example, an exception handler for real-time events may require guaranteed fast memory access for specific code and/or data sections. One traditional answer to the need for guaranteed fast memory access has been to add a dedicated high-speed memory either internal or external to the microprocessor substrate. However, a number of disadvantages are inherent in this approach. If the dedicated high-speed memory resides on the microprocessor substrate, its memory capacity is limited by the constraint of conserving semiconductor substrate area. Furthermore, once embedded into the microprocessor substrate, the capacity of the high-speed memory is forever fixed. This is clearly a disadvantage if software applications have varying demands for the high-speed memory. If the dedicated high-speed memory resides external to the microprocessor substrate, its speed generally will not be adequate to allow full speed processing (similar to processing with a 100% cache hit rate).
Another solution to the problem of providing guaranteed fast memory access is afforded by cache memories which allow a line by line locking mechanism. Locking a cache line corresponding to a given address tag implies that the line will not be deallocated by the cache memory. Generally, the microprocessor (or microprocessor core) asserts a write cycle to ensure the allocation of a cache line corresponding to a desired address, and then locks the cache line. All future reads and writes to the address range given by the locked cache line will be satisfied directly from the cache memory.
Furthermore, by locking a plurality of cache lines, a reserved area of the data cache is created which functions as a dedicated fast access internal memory. The access time to the reserved area is equal to the cache hit access time. And the size of the reserved area may be configured to match the requirements of the processing task being performed. However, for write-through cache memories, write accesses to the reserved area (i.e. the plurality of locked lines) are presented to the bus interface of the microprocessor and need to be serviced by system memory. Since the reserved area is locked for the duration of the application and will therefore satisfy all future reads directly without accessing system memory, the write through operations to system memory are wasting unnecessary bus cycles, and lowering system performance. Also, the address range (or space) corresponding to the reserved area must be imaged by physical addresses in the external memory system in order to accept the write requests passed through the cache memory. Memory locations mapped to the imaged physical addresses are never read by the data cache and thus are wasted.